Many methods using integrated circuit manufacturing techniques have been used to form capacitors. One such method first forms a highly doped region in a semiconductor substrate to act as a bottom conductive plate of a capacitor and later forms a conductive polysilicon or similar material plate overlying and insulated from the highly doped region to act as an upper plate of the capacitor. One such prior art method and structure is illustrated in FIGS. 1a and 1b.
In FIG. 1a, N- substrate 10, which may be an epitaxial layer or the substrate itself, has formed on it dielectric 14, which may be silicon dioxide (SiO.sub.2) or silicon nitride (Si.sub.3 N.sub.4), having a thickness determined by the desired breakdown voltage and capacitance of the resulting capacitor. The wafer is patterned and a P-type dopant, such as boron, is then implanted into substrate 10 through dielectric 14. The dopants are then driven in to diffuse and activate the dopants to form highly conductive P+ region 16. P+ region 16 is sufficiently doped to ensure voltages applied to plate 18 in FIG. 1b do not deplete or invert region 16.
Dielectric layer 14 may also be grown after the implantation of the P-type dopants.
Next, as illustrated in FIG. 1b, a layer of doped polysilicon 18 is deposited over dielectric 14 and etched to form a top plate of the resulting capacitor over diffused region 16.
Insulating layer 20 is then deposited and flowed over the wafer, and metal contact 22 is formed to electrically contact P+ diffused region 16. Insulation layer 20 electrically insulates metal contact 22 from polysilicon plate 18. A separate contact (not shown) is also formed elsewhere on the wafer to contact conductive polysilicon plate 18.
The conductivity types in the example of FIGS. 1a and 1b may be made opposite to that shown while still forming a practical capacitor.
FIG. 2a shows a depletion type MOS device, which may be used as a capacitor, whose channel conductivity is controlled by the gate/source voltage (V.sub.GS). In FIG. 2a, the capacitor consists of polysilicon plate 24, P-substrate 25, N+ contact regions 26 and 27, and N--channel region 28. The capacitance value of this device changes, however, with the level of V.sub.GS, since negative values of V.sub.GS deplete and can invert channel region 28, thereby changing the effective area of the lower capacitor plate and the distance between the upper and lower capacitor plates.
FIG. 2b shows an enhancement type MOS device, which may also be used as a capacitor. A positive V.sub.GS is required to cause the channel region under gate 29 to become conductive so as to act as a lower plate of the capacitor in conjunction with N+ contact regions 30 and 31. Thus, the capacitance of this device also varies with V.sub.GS in a way similar to that described with respect to the depletion type MOS device of FIG. 2a.
An additional drawback of the capacitors of FIGS. 2a and 2b is that for V.sub.GS values below a certain voltage, the channel region of the capacitors of FIGS. 2a and 2b causes the capacitors to have an undesirable high series resistance.
Since the capacitors of FIGS. 2a and 2b are identical to MOS transistors, no additional process steps are used to form these capacitors on a wafer containing identically formed MOS transistors. For this reason, these capacitors are often used, despite their shortcomings, in some non-critical applications.
As seen, the capacitor structures of FIGS. 2a and 2b have a number of drawbacks which the capacitor of FIG. 1b overcomes.
Although the method illustrated in FIGS. 1a and 1b results in a stable capacitor having a highly conductive diffused region as a bottom plate of the capacitor, it is more desirable to form this type of capacitor by using the same masks and process steps which are used for forming MOS transistors on the same wafer. In this more desirable prior art method, the same oxide layer grown for the dielectric of the capacitor is also used for the gate oxide in the MOS transistors. Further, the polysilicon plate of the capacitor is formed by the same steps used to form the polysilicon gates of the MOS transistors. In this more desirable prior art method, however, one extra patterning step and dopant deposition step is required, which is not used in a normal polysilicon gate MOS process, to form the highly doped diffused region, such as P+ region 16 in FIG. 1a, which will act as the bottom plate of the capacitor.
An example of such a process is shown in FIGS. 3a-3c.
As illustrated in FIG. 3a, the surface of N-substrate 32 is patterned, and P-type dopants, such as boron, are implanted or otherwise deposited into N- substrate 32. Dopants may instead be implanted directly through a thin oxide layer, such as later formed oxide layer 38. The dopants are then driven in to form highly conductive P+ region 33.
Next, as shown in FIG. 3b, N- substrate 32 has grown on its top surface thick field oxide, which is then patterned to form thick oxide regions 36. Gate oxide layer 38 is then grown over the top surface of substrate 32. Oxide layer 38 acts as both the gate oxide for MOS transistors formed on the wafer and the dielectric of the resulting capacitor formed using the below-described procedures.
Also shown in FIG. 3b, polysilicon plate 40, typically doped with phosphorus to lower its resistivity, is formed on oxide layer 38 so that P+ region 33 extends out from under plate 40. At the same time, doped polysilicon gate 42, which will eventually be a gate of an MOS transistor, is also formed.
A thin layer of oxide 46 is then grown over the surface of the wafer, including over polysilicon 40 and 42, to help protect polysilicon 40 and 42 from being reverse doped with P-type dopants.
P-type boron ions are then implanted into the exposed regions of N- substrate 32 around polysilicon 40 and 42 to form source region 50 and drain region 52 self-aligned with respect to polysilicon gate 42 and to form contact regions 54 and 56 self-aligned with polysilicon plate 40 and P+ region 33. The boron ions are driven in at this time or at a later time, depending upon the junction depth desired.
As shown in FIG. 3c, insulating layer 66 is deposited over the surface of the wafer using a conventional process, such as a boron/phosphorus silicon glass (BPSG) technique, and flowed. This step may be preceded by a separate drive-in step for the boron ions. Insulating layer 66 is then selectively etched to form contact holes.
A metal deposition and etch process is then used to form metal contacts 68 for contacting the various diffused regions in N- substrate 32 and for contacting the various polysilicon regions.
In the structure of FIG. 3c, a capacitor is formed by polysilicon plate 40 and P+ diffused region 60, while a P-channel MOS transistor is formed by gate 42, source region 50, drain region 52, and a channel region under gate 42.
Thus, with only a single extra masking step and dopant implantation step to form P+ diffused region 33 in FIG. 3a, capacitors may be formed in a wafer along with MOS transistors.
What would be desirable to simplify the above process and reduce its cost is a method to form a polysilicon plate type capacitor using an MOS transistor type process without requiring any additional masking and deposition steps other than those used to form the MOS transistors themselves or used to form other components on the wafer utilizing diffused regions.